Interfacing FPGAs with DDR Memory - Phil's Lab

Опубликовано: 28 Октябрь 2024
на канале: Phil’s Lab

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How to determine FPGA pin-out of DDR interface, connect FPGA to DDR memory module, using Vivado and Memory Interface Generator (MIG) tools (Spartan-7). Including schematic and PCB design tips. PCBWay https://www.pcbway.com

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[LINKS]
FPGA Design Tutorial:    • FPGA Design Tutorial (Verilog, Simula...
Microcontroller on FPGA:    • Microcontroller on FPGA (Microblaze, ...
FPGA + DDR PCB Tutorial:    • FPGA/SoC + DDR PCB Design Tips - Phil...

[TIMESTAMPS]
00:00 Introduction

00:44 Xerxes Rev B Hardware
02:00 Previous Videos

02:25 Altium Designer Free Trial
02:53 PCBWay

03:47 Hardware Overview
06:10 Vivado & MIG
08:06 Choosing Memory Module
10:00 DDR2 Memory Module Schematic
12:31 FPGA Banks
15:37 DDR Pin-Out
17:53 Verify Pin-Out
18:51 Additional Constraints
21:40 Termination & Pull-Down Resistors
22:52 PCB Tips

25:55 Future Video

26:16 Outro