Increasing the integration scale of our processors requires improvements in component and parametric yields, qubit coherence, and readout performance. In this talk, we will highlight the work done by our Chip Architecture and Fabrication team to enable a distance-5 surface code experiment on a 72 qubit processor, specifically in managing yield, performance, and parameter spreads. I will then show data from new parametric amplifier designs that will allow further scaling of our readout subsystem.
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