Verilog A Tutorial: Exploring the Fundamentals and Applications of Verilog A
In this episode, we have explored a range of topics related to Verilog-A, a behavioural modelling language specifically designed for analog circuits within the Verilog Family. Verilog-A serves as a subset of Verilog-AMS and is derived from the IEEE 1364 Verilog HDL specification. The primary objective of Verilog-A HDL is to enable designers of analog systems and integrated circuits to create and utilize modules that encapsulate high-level behavioural descriptions, as well as structural descriptions, of systems and components.
We delved into the reasons behind the creation of Verilog-A, highlighting its purpose and the strong relationship it shares with SPICE, a popular electronic circuit simulator. We also explored various BSIM Compact Models, which play a crucial role in accurately simulating and analyzing integrated circuits.
Furthermore, we discussed the correlation between Verilog, Verilog-A, and Verilog-AMS, shedding light on how these languages work together to provide comprehensive behavioural and structural descriptions for analog systems and components. We explored disciplines/natures from desciplines.vams, providing insights into their significance and role within the Verilog-A modelling approach.
We then delved into the basics of Verilog-A, including its fundamental principles and modelling approaches. This included a deep dive into the conservative modelling approach, which focuses on preserving key characteristics and ensuring robustness in the modelling process. We examined a practical example to illustrate its application. Additionally, we explored the signal flow modelling approach, which emphasizes the flow of signals and interactions between different components, accompanied by an example for better comprehension.
By covering these topics, we aimed to provide a comprehensive understanding of Verilog-A and its relevance in the realm of analog circuit design, equipping viewers with valuable knowledge for their design and modelling endeavors.
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In this video the below topics are covered :
(Click on Time-Stamp & Navigate to the topic directly)
00:00 Beginning of Video
00:23 Episode Intro
00:23 Why Verilog A was created ?
01:32 Strong Bonding between SPICE and Verilog-A
02:56 Various BSIM Compact Models
04:02 BSIM Model in Verilog-A Snippet
05:50 Corelation between Verilog, Verilog-A and Verilog-AMS
09:52 Desciplines/Natures from desciplines.vams Explained
13:09 Verilog-A Basics
15:25 Verilog-A Modeling Approach
17:08 Conservaive Modeling Approach
18:52 Conservaive Modeling : Example
21:09 Conservaive Modeling Example : Multiple Contributions
24:53 Signal Flow Modeling Approach
28:04 Signal Flow Modeling : Example
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Courtesy and Reference :
Music by Bensound.com
Jacob Abbott from Pixabay
Documents & References :
OVI Verilog-A LRM , 1996
A New Approach to Compact Semiconductor device Modelling with Qucs Verilog-A analog module synthesis, M.E Brinson & V Kuznetsov, International Journal of Numnerical Mdelling, 2015
https://github.com/cogenda/VA-BSIM48/...
https://literature.cdn.keysight.com/l...
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