Understanding the Differences Between Synthesizable and Non-Synthesizable Verilog Code | EP-17
This episode delves into the importance of Verilog syntax for synthesis, a key aspect of digital design. The various types of Verilog constructs are thoroughly explored, including fully and partially supported constructs, ignored constructs, and unsupported constructs. Through this comprehensive discussion, viewers gain a deep understanding of Verilog syntax for synthesis and how to apply this knowledge to create functional digital designs that can be synthesized into hardware.
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In this episode we have discussed the below topics :
00:00 Beginning & Intro
00:30 Chapter Index
01:52 Introduction
04:10 Types Of Verilog Syntax for Synthesis
07:11 Fully Supported Verilog Constructs
08:36 Partially Supported Constructs
10:50 Ignored Constructs
12:22 Unsupported Constructs
#verilog
#synthesis
#vlsi
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References, Acknowledgements & Credits :
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