Verilog A Tutorial: Exploring the Fundamentals and Applications of Verilog A
In this episode, we have covered a comprehensive range of topics related to Verilog-A, a powerful behavioural modelling language specifically designed for analog circuits within the Verilog Family. It serves as a subset of Verilog-AMS and is derived from the IEEE 1364 Verilog HDL specification. Verilog-A HDL empowers designers of analog systems and integrated circuits by providing a platform to create and utilize modules that encapsulate both high-level behavioural descriptions and structural descriptions of systems and components.
The episode delves into various aspects, including a detailed comparison between Verilog and Verilog-A, the utilization of display functions such as $strobe, $write, $display, and $monitor, and the exploration of control structures and loops. We explore conditional constructs such as if-else, if-else-if, and various operators such as logical, arithmetic, bit-wise, and relational operators. Additionally, we examine the case statement, repeat statement, while loop, for loop, forever loop, and the generate statement.
Furthermore, we delve into the process of generating and flattening statements after compile and elaboration. We explore the concept of functions, covering both user-defined functions with their restrictions and examples, as well as predefined functions and signal access functions. The episode also explores analog operators, also known as analog filters, including their restrictions, the delay operator, absolute delay operator, transition operator, and slew operator.
Moreover, we discuss analog events, such as @initial_step and @final_step, and their usage in examples. We also explore the monitoring event with @cross and time point-specific events with @timer. Lastly, we delve into a composite example that combines @initial_step, @timer, and @final_step to showcase the practical application of these concepts in Verilog-A.
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Chapters for easy navigation :
00:00 Beginning of Video
00:18 Intro of this episode
00:58 Verilog Vs Verilog-A Comparison
02:52 Display Functions ($strobe, $write , $display, $monitor)
04:27 Control Structures and Loops
04:44 If-Else
05:32 If & Else-If
07:51 Operators : Logical , Arithmetic , Bit-wise , Relational
09:25 Case Statement
11:20 Repeat Statement
12:32 While Loop
13:44 For Loop
14:48 Forever Loop
16:29 Generate Statement
19:59 Generate Statement Flattening after Compile & Elaboration
21:01 Functions Chapter Begin
21:18 User Defined Function
23:03 User Defined Function : Restrictions
23:23 user Defined Function : Example
25:09 Predefined Functions
25:48 Signal Access Functions
27:25 Analog Operators a.k.a Aalog Filters
28:48 Analog Operators : Restrictions
30:33 Delay Operator
31:42 Absolute Delay Operator
32:11 Transition Operator a.k.a Transition Filter
34:15 Slew Operator a.k.a Slew Filter
35:34 Analog Events
37:00 Analog Events Chart
38:10 @initial_step & @final_step
39:18 @initial_step : Example
42:05 @cross : monitoring event
44:25 @timer : time point specific event
47:04 Composite Example : @initial_step , @timer & @final_step
#vlsi
#vlsidesign
#verilog
Courtesy and Reference :
Music by Bensound.com
Jacob Abbott from Pixabay
Documents & Referneces :
OVI Verilog-A LRM , 1996
A New Approach to Compact Semiconductor device Modelling with Qucs Verilog-A analog module synthesis, M.E Brinson & V Kuznetsov, International Journal of Numnerical Mdelling, 2015
https://literature.cdn.keysight.com/l...
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