VLSI Project - Resource Shared Crypto Coprocessor of AES Enc/Dec With SHA-3 - ClickMyProject
As CMOS technology reaches its scaling threshold, evolving non-volatile memory (NVM) approaches are becoming a hopeful substitutes to Dynamic RAM (i.e.) DRAM because of the low leakage power and improved scalability. Advanced Encryption Standard (AES) engine, runtime performance and overhead energy are involved.cost-sensitive memory, the intrinsic logic operating capability of NVM was utilized to employ the proposed AESIM technique. S-box is utilized along with AESIM methodology for performing. AESIM technique is calculated for both encryption and decryption process by measuring the minimum time used, the minimum time taken for the time before clock delivery, the average time required for operation after clock, the latency and the amount of logic separately for the proposed AESIM encryption and decryption technique
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