SV-1: Object-oriented Programming for Designers | Synopsys
If you are a digital design engineer working with Verilog or VHDL and are stumped by Object-oriented programming this is the webisode for you. You will see the connection between Verilog module and classes to enable you to use the full power of Object-oriented programming (OOP) to define, run and debug SystemVerilog and UVM based Testbenches.
